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Formal 101 – Setting Up & Optimizing Constraints

May 11, 2021

2 speaker avatar

Constraints development for formal analysis is quite simply the creation of appropriate limits on the universe of possible stimulus being driven into the DUT’s input signals – i.e. it is conceptually similar to a constrained-random RTL simulation stimulus setup. However, in this process, instead of writing formatted constraints in SystemVerilog or VHDL, the user describes valid behavior of the inputs using either hand-written “properties” in SystemVerilog (SVA) or Property Specification Language (PSL), or productized libraries for standard protocols (AHB, AXI, etc — Siemens EDA offers multiple formal-optimized verification IPs.) Furthermore, the unique nature of formal analysis enables engineers to learn important information by temporarily under-constraining and over-constraining the analysis.

In this 40-minute webinar we will show you how to write optimal constraints for formal analysis; and how to deliberately under- and over-constrain the analysis to learn more about the effectiveness of the constraints themselves, your test plan and formal coverage plan, and the DUT behavior.

Note that this webinar will be relatively technical: the examples will include RTL code — familiarity with Verilog or VHDL is assumed.

What You Will Learn:

  • The difference between simulation and formal constraints
  • How “less is more” when it comes to formal constraints
  • How to benefit from deliberately under- and over- constraining the analysis
  • How you can further leverage an aspect of the popular “assume-guarantee” formal principal to further refine your constraints

Who Should Attend:

  • Design & Verification engineers who are new to formal property checking

Product Covered:

Questa PropCheck

Meet the speakers

Photo of Mark Eslinger


Mark Eslinger

Product Engineer

Mark Eslinger is a Product Engineer in the IC Verification Systems division of Siemens EDA where he specializes in assertion-based methods and formal verification. Mark has over 25 years of experience in design and verification, applications engineering, and technical marketing.
Photo of Joe Hupcey


Joe Hupcey

Questa Formal Product Manager

Joe Hupcey III is a part of the Siemens EDA’s Product Management team for Design & Verification Technologies; based in the Silicon Valley, CA. He is responsible for the Questa Formal product line of automated applications and advanced property checking. Prior to joining Siemens EDA, Joe has held product management and marketing roles in several Electronic Design Automation (EDA) companies, for products that covered multiple aspects of hardware and software functional verification. Before transitioning into marketing, Joe worked as an electrical engineer in FPGA design, EDA tools for FPGAs and ASICs, and ASIC verification. Joe’s educational background includes BSEE, MSEE, and MBA degrees from Cornell University in Ithaca, NY.
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