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Electronic Systems SI/IP Forum
April 22, 2021 @ 10:00 AM - 5:00 PM
Title: KEYNOTE: Is Power Integrity the New Black Magic?
Date: Thursday, April 22, 2021
Time: 01:00 PM Eastern Daylight Time
Duration: 1 hour
Electronic Systems SI/PI Forum
KEYNOTE: Is Power Integrity the New Black Magic?
Sponsored by: Cadence
Presented by: Istvan Novak, Principal Signal and Power Integrity Engineer, Samtec
Abstract:
Power integrity (PI) is a relatively new discipline, emerging after electromagnetic compatibility (EMC) and signal integrity (SI), and is quickly becoming the key challenge for system, circuit, board, package, and silicon designers. Some industry experts say that as SI has matured, PI has now become the new black magic. This talk will examine the reasons why PI is so difficult and will analyze past predictions and current challenges. The safety and reliability concerns brought on by the proliferation of power electronic circuits in all walks of life will be discussed, from tiny energy-harvesting circuits, through consumer electronics products, to high-power electronics in autonomous vehicles.
Presenter Bio:
Istvan Novak is a Principal Signal and Power Integrity Engineer at Samtec, working on advanced signal and power integrity designs. Prior to 2018 he was a Distinguished Engineer at SUN Microsystems, later Oracle. He worked on new technology development, advanced power distribution, and signal integrity design and validation methodologies for SUN’s successful workgroup server families. He was engaged in the methodologies, designs and characterization of power-distribution networks from silicon to DC-DC converters. He is a Life Fellow of the IEEE with twenty-nine patents to his name, author of two books on power integrity, teaches signal and power integrity courses, and maintains a popular SI/PI website. Istvan was named Engineer of the Year at DesignCon 2020.
Title: DDR Crosstalk Problems Where You Least Expect Them
Date: Thursday, April 22, 2021
Time: 02:00 PM Eastern Daylight Time
Duration: 1 hour
Electronic Systems SI/PI Forum
DDR Crosstalk Problems Where You Least Expect Them
Sponsored by: Cadence
Presented by: Jayaprakash Balachandran, Technical Lead, Cisco and Hannah Bian, Signal Integrity Engineer, Cisco
Abstract:
The lighting fast speeds of double-data-rate 5 (DDR5) data, require many signal integrity (SI) engineers to invest significant analysis time ensuring that data signals will meet the bit error rate (BER) and mask requirements associated with the Joint Electron Device Engineering Council (JEDEC) data bus specification. This talk will show that while the data bus gets all the glory, there are other parts of DDR design and analysis that also deserve attention. Join this presentation to see how Cisco engineers spend part of their DDR analysis time and were able to uncover a problem before the prototype stage, thereby avoiding a costly respin of a PCB.
Presenter’s Bio:
Jayaprakash Balachandran (JP) is with Unified Compute Server (UCS) Group at Cisco Systems Inc. JP has over 16 years of experience in high-speed design and has a PhD from KUL/IMEC Belgium. He has many peer reviewed publications and leading PoC workstream in OCP/ODSA.
Hannah Bian got MSEE from Southeast University China, major in RF IC design. She is with Cisco as Signal Integrity Engineer working on UCS server designs since 2014. She covers high speed serial IO and DDR3/4/5 channel modeling and analysis. Other professional interests include exploring new SI/PI analysis flows and methodologies to accelerate the product development cycle.
Title: FastPI using Standard PI Models to Expedite Platform PDN Design Optimization and Sign-off
Date: Thursday, April 22, 2021
Time: 03:00 PM Eastern Daylight Time
Duration: 1 hour
Electronic Systems SI/PI Forum
FastPI using Standard PI Models to Expedite Platform PDN Design Optimization and Sign-off
Sponsored by: Cadence
Presented by: Kinger Cai, Platform Electrical Architect, Intel Corp
Abstract:
PCB design cycles are being accelerated with the FastPI streamlined platform power distribution network (PDN) design architecture, which provides distributed computing on private or public clouds upon a standard power integrity model (SPIM) that includes scalable unified PI target (UPIT) and compact voltage regulator model (CVRM) models. With automated design optimization, review and signoff can be expedited to address multi-layer ceramic capacitor (MLCC) shortages and deviated power delivery networks (PDNs) in the designs of Intel customer TTM Technologies. Cost, performance, stackup, and physical dimension tradoffs are enabled with a Cadence design and analysis framework featuring Cadence® Allegro® and Sigrity™ technology upon FastPI with Intel SPIM and CVRM products.
Presenter Bio:
Kinger Cai is currently leading platform electrical architecture and design for both next generation CPU and discrete GPU facilitating I+I platform strategy in Client Computing Group in Intel Corp. Over the last 20 years, Kinger led developing several generations of client, media and mobile platforms. Kinger acquired Ph. D from Shanghai Jiao Tong university in 2001 and MBA degree from W.P Carey business school of ASU in 2008. Kinger published over 30 papers, and 14 patents with 6 granted in the US.
Title: Sigrity 2021: 10X Performance for Next-Gen SI/PI
Date: Thursday, April 22, 2021
Time: 04:00 PM Eastern Daylight Time
Duration: 1 hour
Electronic Systems SI/PI Forum
Sigrity 2021: 10X Performance for Next-Gen SI/PI
Sponsored by: Cadence
Presented by: Ken Willis, Product Engineering Group Director, Cadence
Abstract:
Cadence® Sigrity™ 2021, the latest signal integrity (SI)/power integrity (PI) software release, includes faster engines, distributed computing, and a new user interface. In addition, a new methodology for performing PI across multiple fabrics is now available. This presentation will introduce how the new Sigrity X-Technology distributed computing architecture is meeting the demands of SI/PI engineers across the 5G communications, automotive, hyperscale computing, and aerospace and defense industries.
Presenter Bio:
Ken Willis is a Product Engineering Group Director focusing on system-level analysis solutions at Cadence Design Systems. He has over 30 years of experience in the modeling, analysis, design, and fabrication of high-speed digital circuits. Prior to Cadence, Ken held engineering, technical marketing, and management positions with the Tyco Printed Circuit Group, Compaq Computers, Sirocco Systems, Sycamore Networks, and Sigrity.
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