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Early AXI4 SOC Performance Verification Using NVIDIA Matchlib and Catapult SystemC HLS
December 10, 2019 @ 10:00 AM - 11:00 AM
Register For This Web Seminar
10:00 AM – 11:00 AM US/Pacific
NVIDIA Matchlib is a new open source library that enables much faster design and verification of SOCs using High-Level Synthesis (HLS). One of the primary objectives of Matchlib is to enable performance accurate modeling of SOCs in SystemC/C++. With these models, designers can identify and resolve issues such as bus and memory contention, arbitration strategies, and optimal AXI4 interconnect structure at a much higher level of abstraction than RTL. In addition, much of the system level verification of the SOC can occur in SystemC/C++, before RTL is even created. Once the architectural performance is verified, this flow provides a fully automated flow to silicon using Catapult HLS. This webinar will introduce NVIDIA Matchlib and its usage with Catapult HLS using some AXI4 SOC demonstration examples.
What You Will Learn
- Introduction to NVIDIA Matchlib
- What is motivating a change in design and verification flow complexity
- How risk/complexity in many of today’s SOCs differs from the past
- How to write HLS models using NVIDIA Matchlib
- How Matchlib significantly improves simulation speed and verification efficiency
- Where to find more information and examples for Matchlib from Mentor and NVIDIA
Stuart SwanStuart Swan is an HLS Technologist in the Mentor Catapult team, focusing on SoC modeling for High-Level Synthesis. Prior to Mentor, Stuart worked for Qualcomm and Cadence. Stuart is co-author of the first book on SystemC, “System Design with SystemC,” and was the IEEE technical chairman of the 2005 SystemC LRM. He received his BSEE from Stanford University.
Who Should Attend
- RTL designers, hardware architects, and managers interested in moving up to HLS