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DVCon Japan 2022

June 23

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Welcome to DVCon Japan 2022

Virtual Conference

JUNE 23, 2022

Design & Verification Conference & Exhibition is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits. The conference consists of highly technical content, focusing on the practical aspects of design and verification technology and its use in cutting-edge projects. By having participants refer to and adopt similar technologies, we aim to promote improvements in their own design and verification flow, which in turn raises the technological level of the industry as a whole.

I’m sure many of you are designing in VHDL or Verilog HDL. Both are IEEE standard languages, and it is important to learn their language specifications, but that alone cannot effectively advance design, design capitalization, logic synthesis, simulation, and functional verification. Practical evaluation and acquisition of the advantages and disadvantages that differ depending on various descriptions, including the subsequent processes, are indispensable. The community created for the purpose of learning it efficiently as an industry is the VHDL User’s Group since 1988 and the International Verilog Conference since 1992. The two communities merged into the HDL Conference in 1999 and became the DVCon-Design and Verification Conference in 2003. It is a conference that focuses not only on HDL design but also on the aspect of functional verification, which is an extremely important issue. The current DVCon has a wide range of fields to discuss, such as IEEE standards SystemVerilog, UVM, UPF, formal verification methodologies, Portable Stimulus Standard, SystemC, IP-XACT, functional safety, and security.

With this background, DVCon has established itself as an international conference held not only in the United States, but also in Europe, India, and China. And in 2022, we will hold the long-awaited DVCon Japan. First of all, it will start as an online virtual conference. We would like to ask many engineers and managers to actively participate through further sponsorship through treatises and tutorials.

DVCon Japan 2022 Executive Committee Chief Genichi Tanaka

EXEC TOPICS

Verification and Validation

  • Latest verification methodologies and test benches
  • Verification process, regression testing and resource management
  • Debugging and analysis techniques for complex designs
  • Design and verification using multiple languages
  • Co-design and verification of hardware / software in embedded systems

 Design and Verification Reuse / Automation

  • Connectivity and consistency of validation and validation across multiple verification engines
  • SoC and IP integration method
  • Applying Accellera’s PSS (Portable Stimulus Standard) standard
  • IP configuration management and abstraction
  • High-level synthesis and high-level verification from the ESL language
  • Connectivity and consistency between virtual prototypes, simulations, emulations, and FPGA prototypes

 Machine Learning and Big Data

  • Verification process optimization and its automation
  • Coverage indicators and big data analysis
  • Performance modeling and analysis

 Low-Power Design and Verification

  • Low power design and its verification
  • Verification of clock domain crossing
  • Power modeling, estimation and power management

 Safety-Critical Design and Verification

  • DO-254 compliance and verification
  • Design and verification challenges in ISO 26262
  • Verification challenges in medical and industrial equipment
  • Requiremenets-Driven validation methodology
  • IP Intellectual Property Protection and Security

Mixed-Signal Design and Verification

  • Mixed-signal design and verification techniques
  • Real Number modeling approach
  • UVM extension and application of mixed signal

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Details

Date:
June 23
Event Tags:
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Website:
https://www.dvcon-jpn.org/

Organizers

Accellera
Cadence
Synopsys
Siemens EDA

Venue

Online