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DVClub Silicon Valley
February 7, 2020 @ 11:30 AM - 2:00 PM
Guest Speakers: Dave Rich (Mentor), Cliff Cummings (Sunburst Design)
Please join us for DVClub’s 2020 kickoff event on February 7, 2020 at Dave and Buster’s in Milpitas!
We are happy to announce that Dave Rich, a member of the Flows and Methodology Product Engineering team at Mentor, a Siemens Business, and Cliff Cummings, President of Sunburst Design will be presenting.
- 11:30am — Doors Open / Networking
- 12:00pm — Lunch / Presentations by Dave Rich and Cliff Cummings
- 1:30pm — Networking
“SystemVerilog Random Constraints Demystified” by Dave Rich (Mentor, a Siemens Business)
Constrained Random Verification (CRV) addresses the time-consuming task of writing individual directed tests for complex systems. We sometimes say that CRV automates writing tests for quickly producing the test cases you can think of, or hitting the corner cases you didn’t. But the reality is, like with any computer programming language, your code executes exactly the way it is written, and has no concern for what you were thinking. In particular when coding constraints, this manifests as results that satisfy the constraints, but may not match what you intend. This talk will identify one of the most basic misunderstandings about why you get unexpected results: Not understanding the rules behind Verilog expression evaluation.
- Dave Rich is member of the Flows and Methodology Product Engineering team. He is chartered with streamlining our testbench flows as they interact with a number of Mentor’s products, especially around the Questa Simulation platform. Dave brings over three decades of design and verification experience to bear on developing advanced verification methodologies. He has been actively involved in the standardization of SystemVerilog, via Accellera and then the IEEE, where he has served as co- chair of the Technical Champions committee in the SystemVerilog IEEE 1800 Working Group. At Mentor Graphics, Dave was one of the original designers of the Advanced Verification Methodology (AVM), and later the Open Verification Methodology (OVM). Recently, Dave was working for the Mentor Consulting Division where he was driving the adoption of our simulation technologies with various customers. Prior to that, Dave worked on early simulation and synthesis technologies at Cadence and Synopsys.
“UVM Virtual Sequence Techniques” by Cliff Cummings (Sunburst Design, Inc.)
What are virtual sequencers and virtuals seqences and when should they be used?
Tests that require coordinated generation of stimulus using multiple driving agents benefit from using virtual sequences.
This presentation will describe two different Virtual Sequence techniques and the pros and cons of each. This presentation will also detail the m sequencer and p sequencer handles and the macros and methods that are used with these handles. The objective of this presentation is to clarify different approaches to using virtual sequencers and virtual sequences.
- Cliff Cummings is President of Sunburst Design, Inc., a company that specializes in world-class SystemVerilog, Synthesis and UVM Verification training. Cliff has presented hundreds of SystemVerilog seminars and training classes and has been a featured speaker at multiple world-wide SystemVerilog and Assertion Based Verification seminars. Cliff has been an active participant on every IEEE Verilog and SystemVerilog committee, and has presented more than 50 papers on Verilog & SystemVerilog related design, synthesis, and OVM/UVM verification techniques, including more than 20 that were voted “Best Paper.” Cliff holds a BSEE from Brigham Young University and an MSEE from Oregon State University.