Driving Low-Power Design with High-Level Synthesis
July 7 @ 11:00 AM - 12:00 PM
With the growth in computing at the edge driven by the explosion of battery-powered smart devices, designing for low power is mission-critical to product success. Numerous techniques, spanning all stages of design, are employed to reduce power. Since many of the low-power design techniques come at a cost in performance, the key design challenge continues to be how to optimize for low power while meeting performance goals. This webinar shows how power intent is first captured at the system level and how low-power techniques are automatically applied at each stage where power, performance, and area are concurrently optimized through implementation.
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