DFT India Tech Day

Overview

The half day seminar will focus on following key test challenges IC vendors face as they involve in enabling high test quality on complex application specific designs.

• Design augmentation to detect, mitigate and eliminate security, functional safety, device early failure and wear-out risks
• Effective use of realistic fault modeling to gather precise information on defect distribution and detection.
• Meeting high automotive test coverage goals within expected time budgets
• Extracting value from Tessent Connect platform to achieve high implementation efficiency
• DFT Tips and Tricks
• Customer Experiences

What You Will Learn

This half-day seminar will focus on key test challenges IC vendors face as they try to make the promises of the autonomous age a reality.

The world of ATPG just changed with the introduction of a new solution that can calculate the critical-area effectiveness of each test pattern. Knowing the likelihood of detecting defects based on their critical area, combined with pattern sorting between various pattern sets, lets users choose the most effective test patterns to apply.

The growth of electronics in automobiles has spurred significant innovation in the development of advanced safety mechanisms for all the electrical and electronic systems in a vehicle. In addition to very high-quality manufacturing test, ICs for safety-critical applications need in-system test to detect faults and monitor circuit aging. Scan-based logic built-in-self-test (LBIST) is the technique used for in-system test, but traditional LBIST often can’t meet the coverage goals within the required diagnostic test time interval (DTTI). This talk will look at the current challenges and introduce new DFT technique to the overcome the problem.

EDA companies used to supply discrete DFT tools for ATPG, or memory BIST, or other functions.  Semiconductor DFT teams have traditionally been developed with the overall device in mind and were responsible for the SoC level integration. This is no longer possible. DFT for modern SoCs requires methodologies to address design scaling with plug-and-play principles and automation.  The Tessent platform was developed over many years to solve these issues by providing one common tool and common database which includes various DFT functions such as ATPG or BIST as well as top level and hierarchical integration.  As a result, users can achieve a demanding schedule with automation and hierarchical/SoC level integration.  The DFT methodologies described here are designed to address continued design scaling with plug-and-play principles and automation.

ABOUT THE PRESENTERS

Lee Harrison is Automotive IC Test Solutions Manager, with Mentor, A Siemens Business. He has over 20 years of industry experience with Mentor DFT products and has been involved in the specification of new test features and methodologies for Mentor customers, delivering high quality DFT solutions. With a focus on Automotive, Lee is working to ensure that current and future DFT requirements of Mentor’s Automotive customers are understood and met. Lee Received his BEng in MicroElectronic Engineering from Brunel University London in 1996.

Ron Press is the technology enablement director of the Tessent product family at Mentor, A Siemens Business. As a 30-year veteran of the test and DFT industry, Ron has presented seminars on DFT and test throughout the world. He is a member of the International Test Conference (ITC) Steering Committee, and a Golden Core member of the IEEE Computer Society, and a Senior Member of IEEE. Ron has patents on reduced-pin-count testing, glitch-free clock switching, and on 3D DFT.   Ron started his work in the test industry at Raytheon Company working on test and consulting throughout the company on test and built-in test. He co-developed the Testability Design Rating System (TDRS) for the US Air Force and received the Raytheon inventor’s award for a system built-in test analysis system. Ron led the development of a state-of-the-art RF/digital tester at Harris RF starting in 1995. He joined the Mentor DFT organization in 1997.

Who Should Attend

All DFT test and product engineers and management who are interested in high quality at lowest test cost. Understanding emerging technologies in Design for Test to enhance quality while simultaneously managing cost.