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Designing SerDes Channels for Protocol Compliance
August 18, 2020 @ 10:00 AM - 11:00 AM
Multi-gigabit serial channels present some of the most stringent signal integrity challenges facing designers today. With high speed links, small details are critical – device pinout, breakout routing, signal routing layers, return paths and parasitics associated with blocking capacitors all have significant impact on channel margin that requires careful design analysis and optimization. Equally important is avoiding analytical overkill – spending too much time optimizing a single structure without considering its impact on total channel margin – because over-optimization wastes time and money.
This webinar explores the different aspects of serial channel design planning and analysis from the pre-layout standpoint, using simulation to develop a detailed set of layout rules. Design of detailed geometries requiring 3D EM simulation is explored, showing how to assess design alternatives and maximize overall channel margin.
What You Will Learn
- SerDes channel concepts & terminology
- Different types of SerDes channel compliance analysis
- Compliance analysis using Channel Operating Margin (COM)
- Evaluating SerDes channels for protocol compliance
- How progressive analysis helps speed the design process
- Creating, parameterizing and analyzing 3D areas
- Optimizing via designs, blocking capacitor and BGA breakouts
- Avoiding analytical overkill by focusing on overall channel margin
Min MaungMin Maung is a Senior Technical Marketing Engineer for HyperLynx Analysis Tools Suite for the Electronic Board Systems segment at Mentor, A Siemens Business. Min has been at Mentor Graphics for over 19 years, holding different positions as Instructional Designer, Instructor, and Corporate Applications Engineer. Prior to Mentor, Min was involved in high-speed PCB designs at an industrial computer company. Min holds a Bachelor of Science in Electrical Engineering from the Michigan Technological University and Masters of Science in Electrical and Computer Engineering from Portland State University.
Todd WesterhoffTodd Westerhoff is the Product Marketing Manager for High-Speed and Analog/Mixed-Signal System Design for the Electronic Board Systems segment at Mentor, A Siemens Business. Todd has over 40 years of experience in modeling and simulation, including 22 years of signal integrity experience. Prior to joining Mentor, he held senior technical and management positions for SiSoft, Cisco and Cadence, and also worked as an independent signal integrity consultant. Todd holds a B.E.E.E. degree from the Stevens Institute of Technology in Hoboken, NJ.
Who Should Attend
- PCB/System Designers
- Engineering Managers
- Signal Integrity Specialists
- PCB Layout Designers