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DDR to Hyperlynx Webinar

January 15 @ 9:00 AM - 10:00 AM

Online – Jan 15, 2020
9:00 AM – 10:00 AM US/Pacific

REGISTER HERE

Overview

This webinar will show the powerful combination of Xpedition Layout routing and HyperLynx SI DDRx Wizard batch simulation to produce optimal DDR4 memory routing in your design. The basic steps will include routing the DDR circuit and simulating the layout in HyperLynx SI.  The process includes providing details to Electrical Engineer and ECAD Designer so DDR will be “Correct by Construction” on the very first fabrication. Simulation allows you to find things that could be problems in a complicated layout. Learn how to set up rules so you have a proper set of routing constraints in Xpedition Layout for the DDR Circuit that will work 100% of the time in HyperLynx SI.

Learn Design Methodologies in the Constraint Manager that will save valuable time and can help speed up your design process.

What You Will Learn

  • How to use HyperLynx SI to help develop Xpedition Layout Constraints
  • Understanding what happens when HyperLynx SI Runs a DDR batch Simulation
  • “Correct by Construction” Strategies for first fabrication results
  • HyperLynx SI verification of quality Layout before fabrication

Who Should Attend

  • Electrical Engineers
  • SI Engineers
  • PCB Designers on Xpedition Layout
  • Users of Xpedition Designer.

ABOUT THE PRESENTERS

Keith Christensen joined Mentor Graphics after a 35-year career as a PCB designer in the disk drive and aerospace industries. He is now an Customer Application Engineer at Mentor Graphics. His past experience and deep knowledge of Xpedition® constraint management and design strategies allows him to work effectively with both Electrical Engineers and PCB Designers.

Weston BealWeston is a Mentor Product Specialist, delivering advanced HyperLynx solutions to customers.  Weston is responsible for signal and power integrity consulting engagements, performing high speed PCB analysis and making design recommendations. He also specializes in automating HyperLynx design flows and creating custom HyperLynx DRC rules.

Weston received his Bachelor of Science and Master of Engineering in Electrical Engineering from Utah State University. He has worked in signal integrity engineering at Sun Microsystems, Compaq Computer Corp. and was a Sr. Signal Integrity Engineer at Micron Technology. Weston is experienced with IC package design, server design, PCI, and SerDes as well as  S-parameters, SPICE, IBIS and IBIS-AMI.

Organizer

Mentor
Website:
https://www.mentor.com/