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Customers’ Experience Using HLS for Image Processing and AI: Xperi® and SeeCubic®

November 5, 2019 @ 10:00 AM - 11:00 AM


XPERI: A Designer’s Life with HLS

As a company with a history of innovation and experience in computational imaging algorithms, FotoNation is always looking for ways to speed up their development processes. This webinar will discuss two aspects of their experience going from RTL to HLS. The first topic is using HLS for algorithms such as Face Detection that they know well with RTL for comparison. The second is to use HLS to develop new Neural Network accelerators and how HLS could help them get from algorithm to critical FPGA demonstrators in a time which would not be possible with traditional RTL flow.

SeeCubic: Catapult HLS for Ultra-D Display Processing

Ultra-D technology provides a solution for glasses-free autostereoscopic displays that can be used in any display application. Real-time conversion of 2D or 3D (left/right) signals to the Ultra-D format is a key component of the Ultra-D implementation. This conversion is based on innovative depth estimation using our patented proprietary algorithms. When our business development team requested the development of an IP block for this function, we were facing a Catch-22 situation. How do we design an IP block that is suitable for IC integration without information on the semiconductors technology? Furthermore, how do we design it for multiple technologies and enable integration in multiple products with different on-chip infrastructures? In this webinar, we show how Catapult® High-Level Synthesis (HLS) development methodology has enabled this IP block development. We will also illustrate how we executed the project with a relatively small team, resulting in a complete FPGA-based validation platform. And finally, we will share some unexpected lessons and reflect on key organizational success factors.

HLS Seminar Series Wrap-Up:

Quick wrap-up session outlining resources available and how you can learn more about HLS for your application.

This webinar is part 7 of the webinar series “HLS for Vision and Deep Learning Hardware Accelerators

What You Will Learn

  • Two separate customer’s experience using HLS for Image Processing and AI
  • Using HLS for algorithms such as Face Detection with RTL for comparison
  • How to use HLS to develop new Neural Network accelerators
  • How HLS can help get from algorithm to critical FPGA demonstrators faster than with traditional RTL flow
  • How Catapult HLS development methodology has enabled IP block development

Products Covered

Who Should Attend

  • RTL Designers or Project Managers interested in moving up to HLS to improve design and verification productivity.
  • Architects or hardware-aware algorithm developers in the field of image processing, computer vision, machine and deep learning, that are interested in rapid and accurate exploration of power/performance metrics.
  • New project teams with only a few hardware designers and multiple software experts that want to rapidly create high-performance FPGA or ASIC IP for computer vision or deep learning markets.
Bram Riemens

Bram RiemensBram Riemens co-founded SeeCubic B.V. in 2011. This startup develops the Ultra-D technology for 3D viewing without glasses. As System Architect Bram drives research and development of the Ultra-D signal processing technology. Before SeeCubic, Bram worked for 25 years in Philips and NXP Research, where he contributed to innovative video processing algorithms and systems. His research focused in particular on the interaction between algorithmic optimization and various realization means (such as general-purpose processors, domain-specific processors, configurable hardware or function-specific hardware). His work resulted in more than 35 patents and patent applications, contributions to several conference papers and contributions to commercial ICs. During the last years at SeeCubic, Bram has headed the implementation of Depth Estimation algorithms in a Real-Time Conversion IP block. In this system, the pixel number-crunching is implemented in hardware using the Mentor Catapult technology.

Alexandru Radoi

Alexandru RadoiAlexandru Radoi has 7 years of experience as a VLSI engineer at FotoNation (currently XPERI FotoNation).

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