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CORE-V HW and SW in the FPGA environment

August 20 @ 11:00 AM - 11:30 PM

Episode 3 of OpenHW TV will air live on 20th August at 11am EST / 4pm BST / 8am PST and will give a detailed update of work in our HW and SW Task Groups, as well as featuring guest member Ashling.

You will hear from the Chairs of the groups about the work of the SW and HW Task Groups to date, including an outlook to future roadmaps. We look in detail at the open source GNU toolchain for the CORE-V family of RISC-V cores provided by Embecosm, and Ashling will present an in-depth overview and live demonstration of the RiscFree Eclipse based IDE debug interface to the Genesys2 FPGA board.

Don’t miss the opportunity to see the complete CORE-V MCU FPGA development environment and ask your questions in the live Q&A session at the end with our panelists.

Our speakers in this episode and available on the panel for the live Q&A will be:

Jeremy Bennett – CEO at Embecosm and Chair of the Software Task Group at OpenHW Group.

Hugh Pollitt-Smith – Senior Engineer, System Design and Embedded Systems Group Lead at CMC Microsystems / Co-chair of the Hardware Task Group and Co-chair of the University Outreach Task Group at OpenHW Group.

Roisin O’Keeffe – VP Business Development at Ashling

Craig Blackmore – Software Toolchain Engineer at Embecosm

Space is limited so register now for this event or contact andrea.barnard@publitek.com for more information.

Details

Date:
August 20
Time:
11:00 AM - 11:30 PM
Event Categories:
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Website:
https://us02web.zoom.us/webinar/register/WN_DNpfU1JuRQWHAmzVlhqdjA