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Chip-to-Chip Communication (Interlaken-LL) for Enterprise and Cloud
March 19, 2020 @ 11:00 AM - 12:00 PM
Thu, Mar 19, 2020 11:00 AM – 12:00 PM MDT
** Work email address required**
Interlaken chip-to-chip connectivity IP has been used for many years in networking and switching fabrics to move high throughput data between large chips. With advanced technology nodes, increasing chip sizes and CPU cluster-based designs, Interlaken has found a unique spot as the protocol of choice for low latency, high throughput chip-to-chip connectivity. SiFive is extending its 8th generation of Interlaken IP with the introduction of Interlaken-Low Latency (LL) IP, which will enable low latency chip-to-chip connectivity in HPC, AI/ML, enterprise and cloud applications. Interlaken-LL IP can provide up to 256Gbps of reliable and scalable throughput between two chips; whereas the standard Interlaken IP from SiFive provides throughput of up to 1.2Tbps.
As the Director of SoC IP Product Marketing at SiFive, Ketan is responsible for Interlaken, Ethernet, HBM memory and other high-speed interfaces.
As the Senior Director of SoC IP at SiFive, Sundeep leads the company’s IP engineering effort and manages the entire soft IP portfolio including Interlaken, Ethernet, HBM, USB, LPDDR controller, and low speed peripherals.
MODERATOR: Daniel Nenni
Daniel has worked in Silicon Valley for the past 30 years with computer manufacturers, electronic design automation software, and semiconductor intellectual property companies. He is the founder of SemiWiki.com.