CadenceTECHTALK: What’s New – PPA and TAT Improvements with Genus and Joules

Time: 09:00 BST / 10:00 CEST / 11:00 EEST & Israel / 13:30 IST

The 22.1 release of the Cadence Genus^™ Synthesis Solution and the Joules^™ RTL Power Solution has many exciting new features and improvements relevant to every SoC designer that wants to improve the power, performance, and area (PPA) and turnaround time (TAT) of their design. In this CadenceTECHTALK^™, we will cover multiple new flows and optimization features. Join us and learn about the new capabilities of our RTL synthesis and power analysis solution.

This webinar will cover the following:

• Congestion-aware synthesis
• Floorplan prediction
• Physical aware synthesis
• Multiple-instantiated-Modulesynthesis
• Smart XOR for power reduction
• Activity-driven analysis and optimization
• Automotive safety implementation using USF
• RTL name mapping LEC flow
• Early clock-gating flow
• xReplay and Glitch Power Analysis
• Power reduction techniques such as ODC and STB gating

Speakers:

Sr Application Engineer, Cadence