
CadenceTECHTALK: What’s New – Novel Advancements in the Innovus Implementation System Part 1
June 13 @ 7:00 AM - 8:00 AM
The 22.1 release of the Cadence® Innovus™ Implementation System has many exciting new features and flows to improve power, performance, and area (PPA), and turnaround time (TAT) during design implementation. Join us in this CadenceTECHTALK™ to learn about the new capabilities of our digital implementation flow:
Part 1 of the webinar will cover the following:
- flashPG – new PG Network Synthesis Flow
- Placement and Pre-CTS updates (place_opt_design turbo)
- Timing and Power Optimization
- Expanded Genus™ Physical Restructuring
- Joules™ xReplay integration for accurate power optimization
- Innovus/Joules XOR Clock Gating Automatic Power Reduction
- Clock Tree Synthesis updates
Part 2 of the webinar will cover the following:
- Routing updates
- Post-Route Optimization updates
- route_opt_design v2
- Early PBA-driven optimization
- Innovus/Pegasus™ In-Design Signoff DRC/LVS/Metal Fill
- Automotive Digital Implementation Flow
IP Lifecycle Management for Chiplet-Based SoCs