CadenceTECHTALK: Via modeling and optimization

Conference Date: June 01, 2022

Meeting time: 14:00 – 15:00 (Beijing time)

As the SERDES link rate continues to increase, it means that the rising edge time continues to decrease, resulting in a gradual increase in the impact of reflections. As the VIA is a location with serious reflections, SI engineers need to optimize the parameters of the high-speed VIA to ensure better performance of the link. But how to model the parameters of VIA in the process of pre-simulation and post-simulation? How to choose suitable parameters? How to pass parameters between layout engineer and SI engineer? Please don’t miss this webinar to learn about the opportunity of Cadence High Speed ​​Structure Optimization (HSSO), we will provide a modeling optimization solution for high-speed vias, and we make the layout engineer and the SI engineer a good relationship between Communication is more reliable. In this webinar, our experts will discuss:

• Design structures force you to understand the importance of high-speed via optimization
• Common factors that affect high-speed VIA performance
• How Cadence Can Help You During Your VIA Pre- and Post-Defense Process
• How Cadence enables reliable data exchange between layout engineers and SI engineers

Lecturer Information:

Lead Application Engineer

Responsible for the technical promotion and support of the Cadence Sigrity product line, providing solutions for customers’ applications in wireless communications, consumer electronics, defense science and industry, chip design and autonomous driving. He has a lot of industry experience and technology accumulation in the SI/PI field.

REGISTER HERE