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CadenceTECHTALK: Static Timing Analysis and Some Important Basics
January 26 @ 7:00 AM - 8:00 AM
Date: Thursday, January 26, 2023
Time: 09:00 GMT / 10:00 CET / 11:00 EET & Israel / 14:30 IST
Static Timing Analysis (STA) aims to validate the timing performance of a synchronous design. While it is a well-known concept in modern digital implementation flows, for engineers who are not familiar with STA or others who would like to refresh their memories, it is sometimes interesting to go back to the basics.
In this webinar, we will discuss STA concepts by defining the basics: delays, timing checks, clocks, exceptions, etc. We will also present the method to describe and constrain these in SDC format. We finally see how SDC constraints are connected to the Cadence® Innovus™ CCOpt™ clock tree engine.
Principal Application Engineer, Cadence