Design teams are facing the challenges of having to add more and more processing and programmable capabilities in their SoC in order to adapt and implement the latest and greatest algorithms during the lifecycle of their products, but at the same time comply with power and thermal dissipation envelops for their products.

Some of the design trade-offs are made at the architectural phase where various hardware and software partitioning options are studied and characterized for power and energy dissipation.

In this presentation, we will describe common challenges and solution in creating an efficient and accelerated flow that will meet technical requirements for accurately measure the power, the energy and system performance while making essential design trade-offs to meet aggressive time-to-market schedule.

Take aways

  • Addressing the challenges of accelerating power and system-level verification in a pre-silicon emulated design flow using Tensilica IP
  • Usability for architecture exploration with Tensilica IP with actual hardware and software implementation
  • Creating an efficient environment to make energy aware trade-offs with accurate implementation characterization data

Date and Time

Wednesday, November 17, 2021
Time: 10:00 AM PDT / 1:00 PM EDT