Low power DRAM is being adopted in a wide array of markets, including automotive, PCs and networking systems built for 5G and AI applications. The specification complexity is increasing to meet higher bandwidth, better performance and extended latencies for multiple use cases. Ensuring that JEDEC low-power double data rate 5 (LPDDR5) specification and overall System on Chip (SoC) requirements are fully met makes verification extremely challenging.

Join us to learn about LPDDR5 verification challenges from IP-level to system-level and demonstrate how these challenges can be significantly mitigated using advanced verification methodologies and tools.

This webinar will cover the following topics:

· Verification challenges of LPDDR5 designs

· IP-level verification for specification’s compliancy

· System-level verification in simulation and emulation


Tuesday, November 9, 2021


EMEA and APJ Sessions: 09:00 GMT / 10:00 CET / 11:00 EET and Israel / 14:30 IST/ 17:00 CST/18:00 JST

North America Session: 10:00 PST / 13:00 EST