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CadenceTECHTALK: Driving Low-Power Design with High-Level Synthesis

October 12 @ 7:00 AM - 8:00 AM

Date: Wednesday, October 12, 2022

Time: 09:00 BST / 10:00 CEST / 11:00 EEST and Israel

With the growth in computing at the edge driven by the explosion in the number of battery-powered smart devices, designing for low power is mission-critical to product success. Numerous techniques, spanning all stages of design, are employed to reduce power. Since many of the low-power design techniques come at a cost in performance, the key design challenge continues to be how to optimize for low power while meeting performance goals. This CadenceTECHTALK™ shows how power intent is first captured at the system level and how low-power techniques are automatically applied at each stage where power, performance, and area are concurrently optimized through implementation.

Register now to find out how to design for low power.

REGISTER HERE

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