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CadenceCONNECT: Building Arm Compute with Cadence Digital Full Flow for Best PPA
April 20, 2021
Arm’s Total Compute approach addresses many different requirements, from low-power edge devices with adequate performance, to data center class processors delivering the highest possible compute throughput. To realize these requirements, there must be a massive shift in the approach to system-on-chip (SoC) design.
CadenceCONNECT: Building Arm Compute with Cadence Digital Full Flow for Best PPA will introduce you to optimized design methodologies for the Arm® Cortex®-X1 and Neoverse™ processors. The event brings together Cadence® and Arm technology users and experts to learn more about how you can efficiently implement your Arm-based SoCs with the Cadence digital full-flow solution and reach your power, performance, and area (PPA) targets. Join us to learn about the latest Arm and Cadence collaboration from experts in each area, with Q&A.
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10:00 AM – 10:20 AMArm Keynote – Collaboration in a Time of Change
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10:20 AM – 10:40 AMCadence Keynote – Building Arm Total Compute for Optimal Performance Within Power Budgets
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10:40 AM – 11:10 AMCustomer Keynote
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11:10 AM – 11:40 AMHow We Pushed Largest 5nm High-Performance Arm Core to 4GHz Frequency
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11:40 AM – 11:50 AMBreak
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11:50 AM – 12:20 AMDivide and Conquer: Hierarchical Methodology to Reduce TAT by 30% or More on Arm’s High-Performance CPU
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12:20 AM – 12:50 PMCPU Design Challenges and Optimizations for ASIC/TV ProductsMediaTek
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12:50 PM – 1:20 PMDelivering Best-in-Class Low Power for Arm Cortex-A78 Mobile 7nm CPU Using the Cadence Digital Flow
TSMC’s First US Fab