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CadenceCONNECT: Building Arm Compute with Cadence Digital Full Flow for Best PPA

April 20

Arm’s Total Compute approach addresses many different requirements, from low-power edge devices with adequate performance, to data center class processors delivering the highest possible compute throughput. To realize these requirements, there must be a massive shift in the approach to system-on-chip (SoC) design.

CadenceCONNECT: Building Arm Compute with Cadence Digital Full Flow for Best PPA will introduce you to optimized design methodologies for the Arm® Cortex®-X1 and Neoverse™ processors. The event brings together Cadence® and Arm technology users and experts to learn more about how you can efficiently implement your Arm-based SoCs with the Cadence digital full-flow solution and reach your power, performance, and area (PPA) targets. Join us to learn about the latest Arm and Cadence collaboration from experts in each area, with Q&A.

Agenda at a Glance
  • 10:00 AM – 10:20 AM
    Arm Keynote – Collaboration in a Time of Change
  • 10:20 AM – 10:40 AM
    Cadence Keynote – Building Arm Total Compute for Optimal Performance Within Power Budgets
  • 10:40 AM – 11:10 AM
    Customer Keynote
  • 11:10 AM – 11:40 AM
    How We Pushed Largest 5nm High-Performance Arm Core to 4GHz Frequency
  • 11:40 AM – 11:50 AM
    Break
  • 11:50 AM – 12:20 AM
    Divide and Conquer: Hierarchical Methodology to Reduce TAT by 30% or More on Arm’s High-Performance CPU
  • 12:20 AM – 12:50 PM
    CPU Design Challenges and Optimizations for ASIC/TV Products
    MediaTek
  • 12:50 PM – 1:20 PM
    Delivering Best-in-Class Low Power for Arm Cortex-A78 Mobile 7nm CPU Using the Cadence Digital Flow

    Register Here

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Date:
April 20
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Cadence
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