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Cadence TECHTALK: Reduce Turnaround Times with an RF/microwave Front-to-Back PCB Workflow

November 10 @ 9:00 AM - 10:00 AM

Date: Thursday, November 10, 2022

Time: 9:00am – 10:00am (PDT)

RF/microwave IP, developed in a specialized design environment, must be transferred to a PCB layout editor where manufacturing constraints, design rule checking (DRC), layout vs. schematic (LVS), and corporate-approved components can be applied and integrated with the power and digital electronics.  The transfer of RF design data (schematic and layout) is often re-entered manually by the layout team using information provided by the RF team, wasting considerable time and effort.

Workflow interoperability between the Cadence® AWR Design Environment® platform and the Allegro® PCB Design editor enables RF and layout teams to share data more efficiently, reducing design turnaround times and avoiding potential errors caused by manual entry. This webinar presents the RF-to-PCB workflow and highlights the ways in which design teams can improve productivity and time to market.

REGISTER HERE

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