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Webinar: Cadence Further Streamlines MMIC, RFIC, and RF SiP Design Workflows

October 18 @ 9:00 AM - 10:00 AM

Date: Tuesday, October 18, 2022

North America Session: 9:00am – 10:00am PT

EMEAI Session: 11:00am – 12:00pm CET

Demand for next-generation wireless communication, aerospace, and transportation systems is driving the need for high-performance, cost-sensitive silicon RFICs and III-V compound semiconductor monolithic microwave integrated circuits (MMICs), often integrated into advanced system-in-package (SiP) modules.

The latest release of the Cadence® AWR Design Environment® platform allows product development teams to meet the challenging performance requirements of these wireless systems in less turnaround time, through a comprehensive RF to mmWave design, EM analysis, and front-to-back work flow interoperability with the Cadence Virtuoso Design Platform.

This webinar will demonstrate key new features that accelerate design entry and platform design sharing to enhance engineering productivity and ensure first-pass success.


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