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Boost Verification Productivity with PSS 2.0 and Perspec

June 10, 2021

June 10, 2021


SoC level verification and validation is often the bottleneck of chip design projects due to lack of methodology and automation for creating system level stimulus and limited content reuse. Complex system use-cases, involve interactions between different elements in the system, are hard to write, model and control manually – in particular when dealing with bare-metal level testing.  Portable Test and Stimulus (PSS) specification 2.0 which was recently released by Accellera, enables creation of abstract models of verification intent that can be used to generate target-specific implementations on a variety of platforms, including simulation, emulation, and virtual as well as FPGA prototypes.

In this webinar, we will review the main principles of PSS 2.0 and demonstrate how Cadence® Perspec™ System Verifier helps to boost productivity of creating SoC level tests by IP level content re-use, automatic use-case amplification and correct-by-construction generation of complex concurrent multi-core/multi-threaded tests.

Date and Time

Thursday, June 10, 2021

Europe and India Session: 14:00 BST / 15.00 CEST/ 16:00 EEST and IDT / 09:00 EDT

NA Session: 16:00 BST / 17:00 CEST/ 18:00 EEST and IDT / 11:00 EDT

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