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Better UVM Debug with Visualizer

June 2, 2020 @ 8:00 AM - 9:00 AM

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Register For This Web Seminar

Online – Jun 2, 2020
8:00 AM – 9:00 AM US/Pacific


Intuitive and easy to use, Visualizer Debug Environment automates debugging for the digital design and verification of today’s complex SoCs and FPGAs.

Find problems in your UVM testbench faster using Visualizer Debug Environment, a high-performance, high-capacity debugger. UVM testbenches can be intuitively debugged in either interactive simulation or post simulation. You will see UVM Objects, UVM Components, Class Instances, transactions and more. Visualizer provides UVM visibility in all windows including the wave window, the source code window, the watch window. Breakpoints can be set, including conditional and instance based.

Learn how you can save time and improve UVM debug techniques.

What You Will Learn

This session will take you through UVM Debug tips and tricks in both Post simulation and Live simulation.

This seminar will provide an overview of UVM debugging techniques:

  • Post simulation
    • In Post simulation, view objects in all windows. As normal in Visualizer, all windows are linked. For example, source code value annotation is available in the source code window, when operating the Class Instance window and selecting an object. Special UVM windows include
      • Class Instances – see all classes created in the simulation
      • UVM Testbench – see the UVM component hierarchy, including derived classes
      • UVM Testbench in a schematic view
      • Tracing a driver from the RTL/DUT into the UVM Testbench
    • Post simulation can view UVM transactions, Verification IP transactions or custom transactions in the waveform window
    • Post simulation waveform window is hyper-linked to the class handles. Double clicking in the waveform opens that specific object instance in the source window with all values.
  • Live simulation
    • Live simulation has all the capabilities of Post simulation, and more
    • Live simulation includes breakpoints, stepping, restart, and checkpoint/restore
    • Live simulation provides a memory usage tracking feature to help find accumulations of class handles that consume excess memory
    • Live simulation provides UVM Configuration and UVM Factory debug


Rich Edelman

Rich EdelmanRich Edelman is a Verification Technologist specializing in helping customers adopt and deploy the UVM and OVM. Rich has worked in ASIC companies, EDA consulting, EDA start-ups, and 2 of the big three. Rich first got involved with the AVM while developing his “RPS training class”, which was an easy way for people to learn about the AVM. Rich’s verification interests range from DPI and transaction recording to register modeling, sequences and class-based debug. Rich has published many related conference papers, including a Best Paper on SystemVerilog DPI at DVCON, and various transaction recording papers with IPSOC. Rich received a BSEE, a BSCS and an MSCS from Washington University in St. Louis.

Who Should Attend

Design & Verification Engineers & Managers

Products Covered

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June 2, 2020
8:00 AM - 9:00 AM
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Mentor Graphics
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