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Best Verifiable QoR – A Formal Equivalence Checking Yardstick

September 8, 2020 @ 10:00 AM - 11:00 AM


To achieve maximal QoR, Broadcom wanted to take advantage of all the advanced optimizations that Design Compiler offers. These optimizations, however, are of little value if they cannot be verified through Formal Equivalence Checking.

This presentation details how Formality Equivalence Checking gave Broadcom the confidence to verify and signoff designs without scaling back or switching off the optimizations or sacrificing PPA goals.

Sathappan Palaniappan
Principal Engineer
Avinash Palepu
Product Marketing Manager

Sathappan Palaniappan works for the ASIC Product Division of Broadcom. His expertise lies in front end design, ranging from architecture, design, RTL coding, synthesis, formal equivalence verification, STA, DFT, and more. He has 5 published patents in audio decoder, Memory PPA optimizations (3) and asynchronous arbiter for masters operating at highly varied dialed frequencies. Sathappan received his Bachelor’s degree in Applied Sciences, Bachelor’s degree in Electronics and Communication Engineering and Master’s degree in VLSI Designs.

Avinash Palepu is the Product Marketing Manager for Formality, Formality ECO and ESP products. Starting with Intel as a Design Engineer, he has held various design, AE management and Product Marketing roles in the semiconductor design and EDA industries. Avinash holds a Master’s degree in EE from Arizona State University and a Bachelor’s degree from Osmania University.

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September 8, 2020
10:00 AM - 11:00 AM
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