Automating Post-Route Verification for Multi-Gigabit Channels

Overview

Performing post-layout verification of multi-gigabit SerDes channels is a challenging but necessary task, because even the most detailed pre-layout simulation studies and routing guidelines can’t anticipate everything. Designs that meet detailed routing requirements can still fail due to discontinuities and resonances that couldn’t have been anticipated.

The large numbers of channels in modern designs makes post-route verification difficult – each channel must be modeled and analyzed individually, which requires an automated, efficient process to be successful. Once modeled, each channel must be analyzed for compliance with protocol requirements in the same automated fashion. This webinar will discuss requirements for effective SerDes channel post-route verification and show how they can be achieved.

What You Will Learn

• Different types of SerDes compliance analysis
• Compliance analysis using Channel Operating Margin (COM)
• Differences between COM analysis and IBIS-AMI simulation
• Different forms of Tx/Rx equalization and when they are effective
• How to identify areas of a SerDes channel that require 3D EM modeling
• How to isolate individual physical effects and determine their effect on system margin
• How to perform post-layout “what if” analysis for SerDes channels
• How to determine the impact of crosstalk on SerDes channel margins

ABOUT THE PRESENTERS

Min MaungMin Maung is a Senior Technical Marketing Engineer for HyperLynx Analysis Tools Suite for the Electronic Board Systems segment at Mentor, A Siemens Business. Min has been at Mentor Graphics for over 19 years, holding different positions as Instructional Designer, Instructor, and Corporate Applications Engineer. Prior to Mentor, Min was involved in high-speed PCB designs at an industrial computer company. Min holds a Bachelor of Science in Electrical Engineering from the Michigan Technological University and Masters of Science in Electrical and Computer Engineering from Portland State University.

Todd WesterhoffTodd Westerhoff is the Product Marketing Manager for High-Speed and Analog/Mixed-Signal System Design for the Electronic Board Systems segment at Mentor, A Siemens Business. Todd has over 40 years of experience in modeling and simulation, including 22 years of signal integrity experience. Prior to joining Mentor, he held senior technical and management positions for SiSoft, Cisco and Cadence, and also worked as an independent signal integrity consultant. Todd holds a B.E.E.E. degree from the Stevens Institute of Technology in Hoboken, NJ.

Who Should Attend

• PCB/System Designers
• Engineering Managers
• Signal Integrity Specialists
• PCB Layout Designers