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ASYNC 2022 Summer School: Gate-level design

June 13, 2022

The steering committee of the IEEE ASYNC symposium is organizing a summer school on asynchronous design.  The goal of the school is to teach asynchronous chip design to students and practitioners interested in digital hardware design.  Participants will learn how to design asynchronous circuits at the behavioral level, gate level, and physical design level using design automation tools and the Skywater 130 open-source PDK.

Registration:  by May 10, 2022
Cost:  free
Note that there are limited seats.  We will notify you by May 20th. Video recordings of the sessions will be made available to all. 

UPDATE 4/22: Due to an incredible response, we have exceeded the number of spaces available for the planned summer school by a large margin.

We are in the process of expanding the number of participants, and will re-open registration once we have the upgraded Zoom license in place. We expect that this will take a few business days. Thank you for your interest!

Format:  Virtual (via Zoom), morning sessions, 9:00am to 1:00pm Eastern Time (US) (Time Zone -4:00 UTC)

Session 1.  June 6: Behavioral design

Session 2.  June 13: Gate-level design

Session 3.  June 20: Physical design

(Please monitor this page frequently for updates)

Expected background: We will assume that attendees are familiar with basic logic design (level of an introductory logic design course that is taught at a University) and/or Boolean algebra/logic. We will also assume familiarity with introductory programming and scripting.

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June 13, 2022
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