Ansys Webinar: Got Clock Jitter? – It’s Worse Than You Think (Asia)

Date and time:

Thursday, July 1, 2021 12:00 am
Eastern Daylight Time (New York, GMT-04:00)

Thursday, July 1, 2021 12:00 pm
Taipei Time (Taipei, GMT+08:00)

Thursday, July 1, 2021 1:00 pm
Korea Time (Seoul, GMT+09:00)

Thursday, July 1, 2021 1:00 pm
Japan Time (Tokyo, GMT+09:00)

Duration: 1 hour

Description:

Today’s advanced SoCs at 16nm and below are faced with increased variation effects as they push for lower power. While transistor sizes continue to shrink with Moore’s Law, threshold voltage scaling is not keeping up. Traditionally, dynamic voltage drop (DvD) signoff and timing signoffare done independently with margins/guard-banding based on historical empirical experience. When designing with the latest silicon processes, this approach can lead to chip failures due to DvD induced jitter on the critical clocks. Ansys provides a comprehensive workflow to model this advanced clock jitter with foundry-certified accuracy for multiphysics simulations across power integrity and variation-aware timing.Join us for this free webinar which provides a detailed analysis of Ansys multiphysics reliability signoff solution for next-generation ultra-low voltage SoCs.Learn how Ansys combines RedHawk-Sc, SeaScape and FX technologies to build a comprehensive Clock Jitter solution that meets the latest industry needs.Discover how this Ansys flow can accurately model dynamic voltage drop impact on clock jitter and let chip designers quickly identify important violations they need to fix to achieve signoff.