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Analyzing Memory Bus to Meet with DDR Specifications
April 14 @ 10:00 AM - 11:00 AM
Part of Simulating for High-Speed Digital Insights series
April 14, 2022 | 10:00 AM PT / 1:00 PM ET
Due to ever increasing data demand, the speed grade for memory is now in the multi-gigabit range. Memory bus design becomes a lot more complicated with tighter design margins due to higher crosstalk between vias and traces along with increased inter-symbol interference. It becomes critical to build up an accurate pre-layout model for the bus, testing it against specifications and optimizing it before spinning another PCB layout. To complete the flow, the same analyses can be applied to post-layout memory buses as well. In this webinar, we will discuss the importance of memory channel pre- and post-layout models, how to build them, and how to optimize them to meet design targets.
- Building Pre-layout memory bus for design space exploration channel models
- Validating Post-layout channel models to the design standard
- Using a wizard-driven smart pre-layout workflow for Data and Command/Address buses.
Product Owner for DDR and SerDes Simulation