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Analog/Mixed-Signal Debug and Visualization Webinar

December 5, 2019 @ 10:00 AM - 11:00 AM



Building a system on a chip requires you to bring 3rd party IP, RTL, Spice netlist, and Post layout netlist files together.

Attend this webinar to learn how quickly you can integrate digital and analog blocks to build a system.


What you will learn:

  • Visualize: Render schematics on the fly from any RTL, Spice, CDL, Calibre and SPEF/DSPF netlists
  • Tracing: Navigate and trace signals easily between digital and analog domains. No need to ascend and descend into cell views
  • Prune: Prune and save critical timing paths/fragments of the design as Verilog or Spice to speed up simulation
  • ERC Checks: Calculate Pin to Pin Resistance, Find decoupling capacitors, Reduce/Filter Parasitics on the net and many more
  • Incomplete design: Can read incomplete RTL designs unlike simulators and synthesis tools
  • Netlist Reduction: Remove clock tree buffers for easier visualization
  • Flat/Hierarchy: Create hierarchy by grouping transistors. Flatten the design or recreate hierarchy on the fly.
  • Export Schematics: To Cadence Virtuoso
  • Documentation: Generate design statistics & reports: Instance & primitive counts. Copy/Paste schematics & signal path into powerpoint for design reviews
  • TCL API: Access to full design database through tcl scripts. Examples include identifying differences in netlists during ECOs.
  • Capacity & Performance: Extremely memory efficient to handle today’s full chip netlists.

Who should attend: 

  • IC Design and Layout Engineers
  • CAD Engineers
  • IP Procurement Teams
  • SOC Integration Teams
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December 5, 2019
10:00 AM - 11:00 AM