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Analog Mixed-Signal and Functional Verification Tech-day
November 6, 2019 @ 9:00 AM - 4:00 PM
Mission-critical applications such as autonomous driving are forcing fundamental changes in the way chips are designed and verified. Most existing methodologies fall short when it comes to accuracy and coverage requirements, leading to over-margining, suboptimal power, performance and area metrics, yield challenges, and silicon failures. However, advancements in machine learning methods have resulted in disruptive improvements in this field, allowing orders of magnitude higher accuracy and coverage than what was previously achievable, with the same compute resources and runtime.
Analog Mixed-Signal Keynote: Machine Learning to Accelerate Electronic Design presented by Amit Gupta, General Manager of the IC Verification Solutions Solido division of Mentor, a Siemens Business.
The Golden Age of machine learning is upon EDA. Over the past four years, we have seen large EDA suppliers and customers grow their internal ML teams and strategies, and ML research projects are emerging in all areas of EDA. But, we have not yet seen much of this investment convert into real production flows and work. This is because it is hard to turn research prototypes into production-ready ML tools that function correctly in the real world. This talk reviews a set of second-order challenges that make it difficult to bring ML solutions to production and discusses approaches for solving them.
Functional Verification Keynote: Mitigating the Effects of Random Hardware Faults for Safe IC Design and Verification.
Everybody wants in on the fast-growing automotive market from traditional tier 1 automotive suppliers to non-traditional fabless semiconductor companies. If you are developing IP or semiconductors targeting this market, you must develop in accordance with ISO 26262 to ensure the safety of your products. The challenge is that this imposes additional development practices, flows and verification needs beyond your normal development practices to ensure products are functionally safe from bit flips and aging. This session will explore the design and verification challenges associated with these random hardware faults in addition to what tools and methodologies are needed to comply with ISO 26262.
What You Will Learn
- Functional Safety trends, applications, and Mentor’s roadmap
- Simulation independent technology advancements: Formal, Verification IP & Portable Stimulus
- Debugging your design across simulation, formal, emulation and prototyping
- Machine learning trends, applications, and Mentor’s roadmap
- Variation-aware design and verification with Solido Variation Designer
- Library characterization and validation with Solido ML Characterization Suite
- Mentor’s New Mixed-Signal Verification Platform Symphony – powered by AFS
- Case studies on methodology, results, and best practices
Who Should Attend
- Analog, Digital, RF and Mixed-Signal designers
- ASIC & FPGA Design and Verification managers
- Library design and characterization teams
- Digital implementation teams interested in library re-characterization and validation
- Analog, RF and Mixed-Signal verification engineers