Analog Design, PDK, Cell library, Parasitic – Analysis Webinar

Learn how to significantly reduce the time needed to troubleshoot the root cause of issues in Analog & Mixed-Signal designs.  Register Today

What you will learn:

• VISUALIZE: Takes SPICE netlist & models & generate clean, easy-to-read transistor-level schematics, circuit fragments, and design documentation to speed up circuit design, debug, and optimization at the transistor-level.
• DESIGN TRACING: Do design exploration with incremental schematic view, quickly extract path between any two points.
• STANDARD CELL LIBRARY/PDKs SPICE NETLIST TO SCHEMATICS: Convert Std Cell library or PDK spice models to clean, human readable schematics, and then import to Cadence Virtuoso via SKILL interface
• PARASITIC: Visualize and analyze parasitic networks (Post layout formats: DSPF, and SPEF), click any net in design and see parasitic network. Find the largest capacitance of D-Net in seconds. Reduce & remove parasitics. Export critical paths for simulation in 3rd party tools.
• CALCULATE PIN-TO-PIN RESISTANCE: Report the pin-to-pin resistance for two pin on the same net without opening a parasitic view.
• CUSTOM DRCs: Easily develop custom DRCs for help in design. Use DRCs like finding floating gates, wrong bulk connections, capacitor like devices, and more.  Access open API for loaded database
• HIERARCHY Vs FLAT: Ability to convert a flat netlist into hierarchy and a hierarchical netlist into flat netlist, and render the modified netlist.
• CIRCUIT PRUNING: Extract, navigate and save critical timing paths/fragments of design as Verilog/Spice/SPEF netlists with the ‘cone/incremental view’, for reuse as IP or external use in partial simulation.
• MIXED SIGNAL TRACING: Trace nets between analog and digital domain, by reading Verilog RTL files, Spice netlist and parasitic in a single view.
• DOCUMENTATION: Generate design statistics & reports for design reviews.
• INTEGRATED ANALOG WAVEFORM VIEWER: Cross probe between schematics and waveforms.

Who should attend:

• Analog Design and Verification Engineers / Managers
• Layout Verification Parasitic Extraction Engineers
• Mixed Signal Design Engineers and Managers
• CAD Engineer
• PDK Developers
• Standard Cell Characterization Engineer

Register Here