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Addressing CMOS Image Sensor (CIS) Verification Challenges

September 23, 2020

Register For This Web Seminar

Online – Sep 23, 2020
8:00 AM – 9:00 AM US/Pacific

Online – Sep 23, 2020
5:00 PM – 6:00 PM US/Pacific


CMOS images sensors (CIS) are now the preferred image sensor across various markets due to the ultra-compact size, high resolution, faster frame rates, low power consumption, and low fabrication cost. Mobile phones, being one of the biggest drivers of demand, now average three cameras per phone and are expected to average four within the next three years. The latest advanced driver-assistance systems (ADAS), in the automotive market, are fueling the need for more sensors including backup cameras, 360-degree surround view, video mirrors, and driver monitoring. Medical imaging is not far behind, with growing demand for specialized image sensors for surgical and other bio-medical applications.

Verification of CMOS image sensors (CIS) is challenging on multiple levels as they contain large arrays of pixels and replicated circuits. CIS have extremely sensitive signal chains, affected by non-uniformities at both the local and global level. Noise is often cited as the most challenging aspect as it impacts the visible quality of an image. Noise along with other factors must also account for variability due to process, voltage, and temperature variation. Image quality and robustness are the key requirements to win market share across various applications. CIS verification requires comprehensive block level characterization for accurate noise analysis and top-level verification to ensure performance and power specs are met in silicon. This webinar will cover some key challenges associated with CMOS Image sensor verification and introduce industry proven solutions and methodologies to address them.

What You Will Learn

  • CMOS Image Sensor Trends and Verification Challenges
  • Methods and tools to correlate Simulation-to-Silicon using Mentor’s Analog FastSPICE
    • Noise characterization
  • How to address CIS mixed signal verification with Mentor Symphony
  • How to perform variation-aware design and verification of CIS with Mentor Solido Variation Designer
Scott GuytonScott Guyton is a Senior Manager, Solutions Architecture in the Analog Mixed-Signal(AMS) Verification Business Unit at Mentor Graphics. Scott joined Mentor in 2014 through the acquisition of Berkeley Design Automation (BDA), where he was Application Engineering Director for Asia. He has over 20 years of experience in IC design and EDA including roles as AE manager at Mentor Graphics and technical account manager at Barcelona Design. Guyton has a BSEE from Cal Poly San Luis Obispo.

Who Should Attend

  • CMOS Image Sensor designer
  • Analog Design Engineer
  • Analog Engineering Manager
  • Analog Verification Engineers
  • Mixed-Signal Circuit Designer
  • CAD Engineers

Products Covered


  • CMOS Image Sensor Trends
  • Verification Challenges
  • Mentor AMS Solutions for Key Verification Challenges
  • CMOS Image Sensor Verification Case Studies
  • Q&A (Live sessions only)
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