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Achieving Low Latency Die-to-Die Connectivity Using a Single Controller and PHY IP Solution
July 15, 2021
Hyperscale data center and HPC SoCs have reached maximum reticle sizes and are processing more data than ever before. SoC designers are exploring alternatives using multi-die solutions to support many use cases such as scaling the SoC compute power for flexibility, splitting the SoC to enable very large SoCs, aggregating functions to reduce power and improve form factor and disaggregating IOs to improve cost and time-to-market. To support such use cases, the most essential task for designers is to implement a high-bandwidth and low latency die-to-die interface. Learn how to implement a reliable 112G die-to-die interface in multi-die SoCs while maintaining the required low-latency using a single controller and PHY IP solution.
Attendees will learn about
- How to enable a reliable die-to-die link with minimum bit error rate
- Advantages of using a single controller and PHY IP solution
Manuel Mota
Sr. Product Marketing Manager
Synopsys
Manuel Mota is responsible for the DesignWare Die-to-Die, High-Speed SerDes, Data Converter and Bluetooth IP product lines. With more than 18 years of technical and marketing experience, Manuel has authored multiple technical papers and presented in several technical conferences on analog and mixed signal design. Prior to Synopsys, Manuel held product marketing, business development, and IP design positions at MIPS Technologies and Chipidea Microelectronica. Manuel holds a PhD in Electronic Engineering from Lisbon Technical University which he completed while working at CERN (Switzerland) as a Research Fellow.
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