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Accelerate Full-Chip Signoff with Massively Parallel Scalability

June 1, 2021


Physical design constraints become a lot more complicated in the advanced nodes, leading to the exponential growth of design rules while adding complexity. Decreasing the active device sizes and higher geometry densities results in increased design rule check (DRC) run time, a big metal fill impact on chip functionality, and greater antenna sensitivity of the gates.

In this CadenceTECHTALK, we will show how the Cadence® Pegasus™ Verification System is addressing these challenges. We will discuss the massive parallel scalability in heterogenous cloud infrastructure, process monitor and recovery, and integration with existing platforms (Cadence’s Innovus™, Virtuoso®, and Allegro® technologies). The advantages of the integrated flows and how they can improve your run-time, accelerate design turnaround time (TAT), and optimize cost is shown.

Date and Time

Tuesday, June 1, 2021

10:00 BST / 11:00 CEST  / 12:00 EEST and IDT / 14:30 IST

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