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Accelerate Early Design Verification for faster Time to Market
June 25 @ 11:00 AM - 12:00 PM
Register For This Web Seminar
11:00 – 12:00 IST
Advanced nodes brings in complexity in designs leading to high Physical verification times with increasing number of DRC errors and more verification iterations. Calibre responds to the need for reduced cycle time with revolutionary new capabilities – Calibre RealTime Digital, Calibre Recon, Calibre Grey Box.
The Calibre RealTime Digital interface provides a tight integration between the Calibre physical verification platform and the digital implementation system.
The Calibre RealTime Digital interface provides immediate feedback on DRC violations during manual DRC fixes, enabling quick and accurate correction of the most complex configurations
Calibre Recon functionality enables physical verification teams to rapidly scan “dirty” designs to methodically find and quickly fix selected classes of errors earlier and faster
Calibre Grey Box functionality helps with early chip verification helping designers to quickly resolve intergration issues using Calibre foundry design kit.
What You Will Learn
- Integrating Calibre DRC in your Digital Implementation Platform
- Smart ways of running DRC on Dirty designs
- Resolve Integration Issues while blocks are still getting ready
- Advanced Debugging Techniques
Nicky RajanNicky holds a Bachelor of Engineering degree (in Electronics and Communication Engineering) from National Institute of Technology, Calicut. Currently working at Mentor Graphics as Application Consultant, she supports advanced technology nodes, various Calibre flows to optimize overall runtimes and efficiency. Prior to Mentor, Nicky has worked with Cadence, Synopsys and GlobalFoundries.
Who Should Attend
- SoC Project Managers
- Physical Verification leads responsible for tape-out
- Block level Physical Design Engineers
- Physical Verification Flow methodology Engineers and CAD Engineers
- Design Engineers
- Design Managers
- CAD Managers