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Accelerate DFT Simulations with Xcelium Multi-Core Technology
May 26, 2021
High-performance DFT simulation is key to completing today’s complex systems on chip (SoCs) on schedule. Because most simulators were developed before the multi-core era, they process Verilog code in a single thread, managing a single active queue of events and handling them one at a time. The serial method in which simulators operate means that each run can take a significant amount of time to complete. Even more computing power will not alleviate the latency problem with serial processing.
The Cadence® Xcelium™ Multi-Core Simulator is a third-generation SystemVerilog simulator that shortens DFT simulation time by breaking the design dependencies into independent parts and then simulating those parts on parallel cores of a server. It automatically partitions the design and dynamically allocates the independent parts across parallel cores of a socket to maximize their usage. The effect is significant acceleration of simulation across designs that are both active and large. The Xcelium Multi-Core Simulator supports full timing annotation, making it also useful for long-latency, high-activity, functional gate-level simulations.
In this webinar, our experts will introduce you to the Xcelium Multi-Core Simulator and present some benchmark results. You will also learn how to qualify functional vectors using the Xcelium Single-Core Simulator and how to get started. In addition, we will share a customer experience case study.
Date and Time
Wednesday, May 26, 2021
Time: 8:00 AM PDT/ 11:00 AM EDT/ 6:00 PM CET