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A Signal Integrity Engineer’s Guide to Successful GDDR6 Design
August 19, 2021
August 19, 2021
As a supplier of GDDR6 design IP for memory controllers, Cadence has a holistic solution of design and analysis tools that implement and simulate the IP in the chip as well as interconnect in the IC package and PCB. The high-performing GDDR6 memory interface is essential to graphics cards, game consoles, high-performance computing (HPC), and machine learning applications. However, it can be quite daunting for a signal integrity engineer to validate a design that will perform at maximum speed. Come explore the successful process where Cadence customers use Clarity and Sigrity X technologies to ensure GDDR6 is implemented to enable maximum performance and minimum cost.
We will cover the ability to model and simulate GDDR6 transmitters, receivers, and the complex interconnect that makes up the GDDR6 interface. Also discussed will be the ability to validate sufficient, efficient, and stable power delivery to the memory controller and memory components.
No matter what memory interface you need to design and simulate, this webinar will help you avoid design respins and reduce the time and cost of getting your design into production.
· GDDR6 overview
· Screening your package and PCB design with in-design analysis
· Overview of the GDDR6 I/O models
· The GDDR6 memory interface testbench for signal integrity
· The GDDR6 memory interface testbench for power integrity
· GDDR6 signal integrity compliance
Date and Time
Thursday, August 19, 2021
Time: 10:00 AM PDT/ 1:00 PM EDT