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A Practical Encounter with UVM Framework
June 26 @ 11:30 am - 12:30 pm
Hosted by Oasis Sales and Trilogic, Inc.
The Universal Verification Methodology (UVM) is a standard verification methodology from the Accellera Systems Initiative that was developed by the verification community for the verification community. UVM represents the latest advancements in verification technology and is designed to enable creation of robust, reusable, interoperable verification IP and testbench components.
UVM Framework is a combination of a class library and a code generator, delivered as part of the Questa® Verification Solution, that enables you to build a UVM testbench within an hour. Providing an architecture and reuse methodology, it allows both experienced and new to UVM verification teams to assemble operational UVM testbenches as well as all the scripts needed to compile and run this testbench. The testbench can also include industry-standard Questa VIP components. This quick jumpstart allows the team to focus on verifying product features instead of the normally tedious work building a UVM TB from scratch.
The ”jumpstart” provided by UVMF produces a UVM compliant template that can be compiled and run immediately into Questa, which is an exciting thing! However, it possesses none the functionality which is residing in the Verification Engineer’s (i.e. architect’s) mind, DUT specification, or the Verification Plan (if any of these exist). This responsibility of customization is now placed squarely in the architect’s hands and becomes the defining task which will, typically, add 20% to the existing code base but take 80% of the entire project time. The later number, estimated here, can vary widely based on the architect’s experience with System Verilog, UVM methodology, and UVMF itself.
This webinar will present a practical encounter with UVMF first time, from the perspective of a limited UVM experience base, focusing (for demonstration purpose) on implementation of the front-end Test Control functionality of the existing MGC Generator Tutorial ALU example design for UVMF.
George StevensGeorge A. Stevens Jr. is a Senior FPGA Verification Engineer at DesignLinx Hardware Solutions, Inc, working as a consultant in the architecting and execution of FPGA Design Verification Environments including System Verilog, UVM, and UVMF technologies. George has been employed, previously, across the DOD and commercial spectrum to include Lockheed Martin, BAE, Arrow Electronics, and Altera in various roles performing Electrical Design, Field Applications Engineering, FPGA Training, and FPGA Verification Engineering. Through DesignLinx he has provide all modes of design verification consulting for many clients to include top tier companies: Xilinx, Raytheon, Northrop Grumman, ADI, Mayo Clinic, L3 Technologies, etc. George lives on the shores of Lake Winnipesauke in Alton Bay NH, and enjoys learning new verification technology, water/snow skiing, professional trumpet playing, and life on a lake. You can reach George at firstname.lastname@example.org.
What You Will Learn
- General UVMF testbench structure and benefits
- The Scenario: “Create a UVM environment from scratch using UVMF”
- Existing Mentor Graphics resources
- Extending Top Test Control within the ALU UVMF example
- Creating new Bench Sequences
- Creating new Verification IP Sequences
- Modifying the Simulation Makefile and running the sim
- General UVMF Conclusion
Who Should Attned
- FPGA/ASIC Design Engineer
- Verification Engineer
- Engineering Managers