3D-IC Chip-Centric Power and Thermal Integrity with High-Performance Hiearchical Analysis

Overview

A 3D-IC includes the package, interposer, multiple chiplets, through-silicon vias (TSVs), and through-dielectric vias (TDVs).  Supplying power to the chiplets and dissipating heat through these various components poses a major power integrity (PI) and thermal integrity challenge. Early analysis also is extremely critical in 3D-ICs since changing the die stack up later in the design process is incredibly challenging or not possible. In this session, get a chip-centric perspective on how to perform PI and thermal integrity analysis in 3D-ICs from early planning to signoff. This talk will cover:

• 3D-IC power grid planning and PI analysis
• 3D-IC early thermal integrity analysis
• 3D-IC chip-centric power integrity signoff with high-performance hierarchical analysis
• Building chip models for 3D-IC system-level power and thermal integrity

Sessions

Date and Time:
Wednesday, March 23

EMEA

9:00 GMT / 10:00 CET / 11:00 EET and Israel / 14:30 IST

North America

10:00am PT / 1:00pm ET

Register Here