Clock gating is one of the simplest ways to reduce dynamic power in a design. By turning off the clock on a register which is busy doing nothing useful you can eliminate pointless switching power in that register and also in much or all of the following fanout cone of combinational logic. In this way, judicious gating can extend battery life and also reduce consequent heating on a device, increasing reliability.
REGISTER HERE for this webinar on September 13[SUP]th[/SUP] at 10am PDT
The trick is – where should you gate? Gating a clock comes with an area cost; it also adds delay or latency in the clock path which can impact timing. Then there’s a question of what signal you will use to gate the clock. Gating which frequently turns off only to quickly turn back on again may actually consume more power than if you hadn’t gated at all. It’s important to look at total power objective when doing this analysis. What set of gating choices, across a range of scenarios, will give you the biggest impact on power with acceptable cost?
Join Synopsys for this webinar in which they show you how to use SpyGlass Power to analyze dynamic power while still at RTL. You will learn how to explore early power estimates using realistic use-cases from simulation files across multiple gating possibilities to find those that will give the biggest return in power saved with lowest impact in other areas.