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Experts Talk: RISC-V CEO Calista Redmond and Maven Silicon CEO Sivakumar P R on RISC-V Open Era of Computing

Experts Talk: RISC-V CEO Calista Redmond and Maven Silicon CEO Sivakumar P R on RISC-V Open Era of Computing
by Daniel Nenni on 04-26-2022 at 10:00 am

Expert talk banner Maven Silicon

India’s top VLSI Training Services company Maven Silicon, a RISC-V Global Training Partner, conducted an insightful discussion with the industry experts Ms. Calista Redmond, CEO, RISC-V International and Mr. Sivakumar P R, CEO, Maven Silicon, on the topic “RISC-V Open Era of Computing”.

To introduce RISC-V, it is a free and … Read More


CEO Interview: Frankwell Lin, Chairman and CEO of Andes Technology

CEO Interview: Frankwell Lin, Chairman and CEO of Andes Technology
by Daniel Nenni on 03-11-2022 at 6:00 am

Frankwell Jyh Ming Lin

Frankwell Lin, Chairman of Andes Technology, started his career being as application engineer in United Microelectronics Corporation (UMC) while UMC was an IDM with its own chip products, he experienced engineering, product planning, sales, and marketing jobs with various product lines in UMC. In 1995, after four years working… Read More


Scalable Verification Solutions at Siemens EDA

Scalable Verification Solutions at Siemens EDA
by Daniel Nenni on 02-24-2022 at 6:00 am

Andy Meier 2

Lauro Rizzatti recently interviewed Andy Meier, product manager in the Scalable Verification Solutions Division at Siemens EDA. Andy is a product manager in the Scalable Verification Solutions Division at Siemens EDA. Andy has held positions in the electronics and high-tech fields during his 20-year career including: Sr.Read More


5 Talks on RISC-V

5 Talks on RISC-V
by Milos Tomic on 12-27-2021 at 6:00 am

Milos Tomic

Veriest recently hosted a webinar focusing on RISC-V as a forerunner of ongoing open-source revolution in chip design. Speakers were distinguished professionals from industry and academia. Webinar covered topics from market trends to open-source hardware initiatives, tools and methodologies.

Zvonimir Bandić: RISC-V Read More


Webinar – Comparing ARM and RISC-V Cores

Webinar – Comparing ARM and RISC-V Cores
by Daniel Payne on 10-14-2021 at 10:00 am

Mirabilis Webinar, October 21

Operating systems and Instruction Set Architectures (ISA) can have long lifespans, and I’ve been an engineering user of many ISAs since the 1970s. For mobile devices I’ve followed the rise to popularity of the ARM architecture, and then more recently the RISC-V ISA which has successfully made the leap from university… Read More


WEBINAR: Architecture Exploration of System-on-chip using VisualSim Hybrid RISC-V and ARM Processor library

WEBINAR: Architecture Exploration of System-on-chip using VisualSim Hybrid RISC-V and ARM Processor library
by Daniel Nenni on 07-26-2021 at 6:00 am

Aug5 TechTalk 2

80% of specification optimization and almost 100% of the performance/power trade-offs can be achieved during architecture exploration of product design.  RISC-V offers a huge opportunity with lots of pipeline and instruction set enhancement opportunities.  Can it really attain the utopian success that people are looking… Read More


StarFive Surpasses Development Goal with the Prodigy Rapid Prototyping System from S2C

StarFive Surpasses Development Goal with the Prodigy Rapid Prototyping System from S2C
by rdgreen on 07-13-2021 at 10:00 am

SartFive

Faced with the challenge of developing a high-performance hardware platform with critical software components, what choices do companies have in rapidly moving their development forward with modest budgets and resources?

That was the challenge faced by StarFive Technology, a leading IP and semiconductor SoC platform solution… Read More


A Free RISC-V CPU Core Builder – Democratizing CPUs

A Free RISC-V CPU Core Builder – Democratizing CPUs
by Steve Hoover on 06-27-2021 at 6:00 am

warp v.org

There are now over a hundred RISC-V CPU cores listed on riscv.org‘s RISC-V Exchange! Amazing. If you need a RISC-V CPU core, you’ll likely be able to find one that suits your needs… if you evaluate a hundred CPU cores to find it.

Or, now, you can configure exactly the core you need, and have it built in seconds, for free! WARP-V Read More


Life in a Formal Verification Lane

Life in a Formal Verification Lane
by Shinavi Shah on 06-22-2021 at 6:00 am

New image for semiwiki

This summer, I got the opportunity to work as a Formal Verification Intern with Axiomise for six weeks. I’m a keen designer and love working in design and architecture. Although, I’ve not started my professional career yet, I have done most of my projects as a designer in my undergraduate and postgraduate studies.

Having said that,… Read More


Software Developers Turn to CacheQ for Multi-Threading CPU Acceleration

Software Developers Turn to CacheQ for Multi-Threading CPU Acceleration
by Lauro Rizzatti on 06-07-2021 at 10:00 am

image001 6

Three-year old CacheQ, founded by two former Xilinx executives and a clever group of engineers, produces a distributed heterogenous compute development environment targeting software developers with limited knowledge of hardware architecture.

The promise of compiler tools for heterogeneous compute systems intrigued… Read More