WP_Term Object
(
    [term_id] => 44
    [name] => IC Knowledge
    [slug] => ic-knowledge
    [term_group] => 0
    [term_taxonomy_id] => 44
    [taxonomy] => category
    [description] => 
    [parent] => 386
    [count] => 89
    [filter] => raw
    [cat_ID] => 44
    [category_count] => 89
    [category_description] => 
    [cat_name] => IC Knowledge
    [category_nicename] => ic-knowledge
    [category_parent] => 386
    [is_post] => 
)
            
IC Knowledge Wiki
WP_Term Object
(
    [term_id] => 44
    [name] => IC Knowledge
    [slug] => ic-knowledge
    [term_group] => 0
    [term_taxonomy_id] => 44
    [taxonomy] => category
    [description] => 
    [parent] => 386
    [count] => 89
    [filter] => raw
    [cat_ID] => 44
    [category_count] => 89
    [category_description] => 
    [cat_name] => IC Knowledge
    [category_nicename] => ic-knowledge
    [category_parent] => 386
    [is_post] => 
)

IEDM 2022 – Imec 4 Track Cell

IEDM 2022 – Imec 4 Track Cell
by Scotten Jones on 01-18-2023 at 6:00 am

2022 IEDM Presentation Session23 2 VictorVega Page 03

At the IEDM conference in December 2022, Imec presented “Semi-damascene Integration of a 2-layer MOL VHV Scaling Booster to Enable 4-track Standard Cells,” I had a chance to not only read the paper and see it presented, but also to interview one of the authors Zsolt Tokie.

Logic designs are built up by standard cells such as inverters,… Read More


IEDM 2022 – TSMC 3nm

IEDM 2022 – TSMC 3nm
by Scotten Jones on 01-02-2023 at 6:00 am

TSMC CPP

TSMC presented two papers on 3nm at the 2022 IEDM; “Critical Process features Enabling Aggressive Contacted Gate Pitch Scaling for 3nm CMOS Technology and Beyond” and “A 3nm CMOS FinFlexTM Platform Technology with Enhanced Power Efficiency and Performance for Mobile SOC and High Performance Computing Applications”.

When … Read More


IEDM 2022 – Ann Kelleher of Intel – Plenary Talk

IEDM 2022 – Ann Kelleher of Intel – Plenary Talk
by Scotten Jones on 12-06-2022 at 10:00 am

Ann 2022 IEDM Plenary Dec. 5 Roadmap Slide

Ann Kelleher is Intel’s Executive Vice President, General Manager, Technology Development, and she gave the first plenary talk to kick off the 2022 IEDM, “Celebrating 75 Years of the Transistor A Look at the Evolution of Moore’s Law Innovation”. I am generally not a fan of plenary talks because I think they are often too broad and… Read More


Does SMIC have 7nm and if so, what does it mean

Does SMIC have 7nm and if so, what does it mean
by Scotten Jones on 09-07-2022 at 10:00 am

SMIC 7nm

Recently TechInsights analyzed a Bitcoin Miner chip fabbed at SMIC and declared SMIC has a 7nm process. There has been some debate as to whether the SMIC process is really 7nm and what it means if it is 7nm. I wanted to discuss the case for and against the process being 7nm, and what I think it means.

First off, I want to say I am not going … Read More


SEMICON West 2022 and the Imec Roadmap

SEMICON West 2022 and the Imec Roadmap
by Scotten Jones on 08-03-2022 at 10:00 am

ITFUSA2022 LucVandenhove Page 093

SEMICON West 2022 was held from July 12th to 14th at the Moscone Center in San Francisco.

On Monday the 11th before the show, Imec held a technology forum at the Marriott Marquee right around the corner from the Moscone center. In recent years the Imec forums have shifted away from the process technology I cover to more of a system and… Read More


IEDM 2022 is shaping up

IEDM 2022 is shaping up
by Scotten Jones on 07-17-2022 at 10:00 am

68th iedm color

IEDM is one of the premiere conferences for the latest information on leading edge semiconductor technology. The 68th annual International Electron Devices Meeting will be held December 3rd through 7th at the San Francisco Hilton.

The paper submission deadline is July 14, 2022, and the late-news deadline is August 22, 2022. … Read More


Imec Buried Power Rail and Backside Power Delivery at VLSI

Imec Buried Power Rail and Backside Power Delivery at VLSI
by Scotten Jones on 06-28-2022 at 6:00 am

Imec BPR Page 06

At the VLSI Technology Symposium Imec presented on Buried Power Rails (BPR) and Backside Power Delivery (BSPD) in a paper entitled: “Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails”. I recently had a chance to interview one of the authors, Naoto Horiguchi about the work. I have interviewed … Read More


ASML EUV Update at SPIE

ASML EUV Update at SPIE
by Scotten Jones on 06-24-2022 at 6:00 am

12051 4 SPIE2022 Smeets 0.33 NA EUV systems for High Volume Manufacturing Page 07

At the 2022 SPIE Advanced Lithography Conference, ASML presented an update on EUV. I recently had a chance to go over the presentations with Mike Lercel of ASML. The following is a summary of our discussions.

0.33 NA

The 0.33 NA EUV systems are the production workhorse systems for leading edge lithography today. 0.33 NA systems are… Read More


Intel 4 Deep Dive

Intel 4 Deep Dive
by Scotten Jones on 06-13-2022 at 6:00 am

Figure 1

As I previously wrote about here, Intel is presenting their Intel 4 process at the VLSI Technology conference. Last Wednesday Bernhard Sell (Ben) from Intel gave the press a briefing on the process and provided us with early access to the paper (embargoed until Sunday 6/12).

“Intel 4 CMOS Technology Featuring Advanced FinFET TransistorsRead More


Intel to present Intel 4 process at the VLSI Technology Symposium

Intel to present Intel 4 process at the VLSI Technology Symposium
by Scotten Jones on 05-20-2022 at 8:00 am

VLSI Symposium 2022 SemiWiki 1

The VLSI Symposium on Technology & Circuits will be held in Hawaii from June 12th to June 17th. You can register for the conference here.

The tip sheet for the conference has been released and one thing that caught my eye is some data from the Intel 4 paper that Intel will be presenting at the conference.

Intel’s old roadmap had 14nm,… Read More