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PSS, Test Realization and Reuse

PSS, Test Realization and Reuse
by Bernard Murphy on 03-31-2020 at 6:00 am

Generating tests from PSS

Mentor just released a white paper on this topic which I confess has taxed my abilities to blog the topic. It’s not that the white paper is not worthy – I’m sure it is. I’m less sure that I’m worthy to blog on such a detailed technical paper. But I’m always up for a challenge, so let’s see what I can make of this, extracting a quick and not very… Read More


Mentor Masterclass on ML SoC Design

Mentor Masterclass on ML SoC Design
by Bernard Murphy on 03-24-2020 at 6:00 am

ML algo design

I was scheduled to attend the Mentor tutorial at DVCon this year. Then coronavirus hit, two big sponsors dropped out and the schedule was shortened to three days. Mentor’s tutorial had to be moved to Wednesday and, as luck would have it, I already had commitments on that day. Mentor kindly sent me the slides and audio from the meeting… Read More


5G SoCs Demand New Verification Approaches

5G SoCs Demand New Verification Approaches
by Mike Gianfagna on 03-16-2020 at 10:00 am

Simplified 4G network

Lately, I’ve been cataloging the number of impossible-to-verify technologies we face. All forms of machine learning and inference applications fall into this category. I’ve yet to see a regression test to prove a chip for an autonomous driving system will do the right thing in all cases. Training data bias is another interesting… Read More


Mentor Helps Mythic Implement Analog Approach to AI

Mentor Helps Mythic Implement Analog Approach to AI
by Tom Simon on 02-27-2020 at 6:00 am

Mythic AMS Verification Challenges

The entire field of Artificial Intelligence (AI) has resulted from what is called “first principles thinking”, where problems are re-examined using a complete reassessment of the underlying issues and potential solutions. It is a testament to how effective this can be that AI is being used for a rapidly expanding number of applications… Read More


High-Level Synthesis at the Edge

High-Level Synthesis at the Edge
by Bernard Murphy on 02-19-2020 at 6:00 am

AI Traditional Hardware Solutions

Custom AI acceleration continues to gather steam. In the cloud, Alibaba has launched its own custom accelerator, following Amazon and Google. Facebook is in the game too and Microsoft has a significant stake in Graphcore. Intel/Mobileye have a strong lock on edge AI in cars and wireless infrastructure builders are adding AI capabilities… Read More


Mentor at DVCON 2020!

Mentor at DVCON 2020!
by Daniel Nenni on 02-17-2020 at 6:00 am

DVCon 2020 SemiWiki

Are you ready for the premier conference for functional design and verification of electronic systems?

Sponsored by Accellera Systems Initiative, DVCon is an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP)… Read More


It’s The Small Stuff That Gets You …

It’s The Small Stuff That Gets You …
by Mike Gianfagna on 02-10-2020 at 6:00 am

Picture2 2

The last session I attended at DesignCon 2020 wasn’t a session at all. Rather it was an interactive discussion with Todd Westerhoff, product manager for electronic board systems at Mentor Graphics. Todd made some observations about the way high-performance PCBs are designed today and perhaps the way they should be designed. … Read More


Bringing Hierarchy to DFT

Bringing Hierarchy to DFT
by Tom Simon on 01-30-2020 at 6:00 am

Tessent Hierarchical Flow

Hierarchy is nearly universally used in the SoC design process to help manage complexity. Dealing with flat logical or physical designs proved unworkable decades ago. However, there were a few places in the flow where flat tools continued to be used. Mentor lead the pack in the years around 1999 in helping the industry move from … Read More


Formal and High-Level Synthesis

Formal and High-Level Synthesis
by Bernard Murphy on 01-22-2020 at 6:00 am

SLEC verification

Formal verification has made significant inroads in RTL and gate-level verification because it provides complementary strengths to conventional dynamic verification methods; using both provides higher levels of coverage and confidence in the correctness of an implementation. I haven’t heard as much about formal use in … Read More


Saving Time in Physical Verification by Reusing Metadata

Saving Time in Physical Verification by Reusing Metadata
by Daniel Payne on 01-08-2020 at 10:00 am

voltage propagation cross reference data min

Physical verification is an important and necessary step in the process to tapeout an IC design, and the foundries define sign-off qualification steps for:

  • Physical validation
  • Circuit validation
  • Reliability verification

This sounds quite reasonable until you actually go through the steps only to discover that some of the … Read More