WP_Term Object
(
    [term_id] => 29
    [name] => Avatar Integrated Systems
    [slug] => avatar-integrated-systems
    [term_group] => 0
    [term_taxonomy_id] => 29
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 3
    [filter] => raw
    [cat_ID] => 29
    [category_count] => 3
    [category_description] => 
    [cat_name] => Avatar Integrated Systems
    [category_nicename] => avatar-integrated-systems
    [category_parent] => 157
    [is_post] => 
)

Detail-Route-Centric Physical Implementation for 7nm

Detail-Route-Centric Physical Implementation for 7nm
by Alex Tan on 10-10-2018 at 12:00 pm

Image RemovedFor many years TSMC has provided IC design implementation guidance as viewed from the process and manufacturing standpoints. The last time TSMC Reference Flow incremented, it was version 12.0 back in 2011. Since then, increased design, process and packaging related complexities of the advanced nodes have demanded… Read More


Apogee Pipelining in Real Time

Apogee Pipelining in Real Time
by Alex Tan on 09-20-2018 at 12:00 pm

Image RemovedPipelining exploits parallelism of sub-processes with intent to achieve a performance gain that otherwise is not possible. A design technique initially embraced at the CPU micro-architectural level, it is achieved by overlapping the execution of previously segregated processor instructions –commonly… Read More


Aprisa and Apogee – The New Avatars

Aprisa and Apogee – The New Avatars
by Alex Tan on 07-19-2018 at 12:00 pm

Image RemovedEarlier physical optimization impacts a design QoR gain and can disclose potential hurdles in dealing with unknown design variants such as new IP inclusion or new process node issues. Along the RTL-to-GDS2 implementation continuum, a left-shift move requires a robust modeling and proper context captures in order… Read More